1. Field of the Invention
This invention relates to a semiconductor device and, more particularly, to a MOS (Metal-Oxide-Silicon) integrated circuit device having an improved bonding pad structure.
2. Description of Related Art
The use of barrier metal technology is inevitable for 0.5 micron designs of semiconductor devices. In a process of fabricating a semiconductor device containing MOS transistors, to which the barrier metal technology is applied, a thick field oxide layer is formed on the substrate to isolate the active regions from each other. The gate electrode of the MOS transistors are generally formed by polysilicon, refractory metal or the like. Typically, an oxide insulation layer, containing phosphorus or boron, is applied to the whole surface of the substrate using a CVD (Chemical Vapor Deposition) method. Openings are formed in the oxide insulation layer to expose the diffusion regions of the transistors.
A barrier metal layer then is deposited over the entire oxide insulation layer, and the exposed diffusion regions. The barrier metal layer serves to prevent solid phase epitaxy in the openings of the integrated circuit device employing a conductive pattern, 0.5 micron in width. Materials for the barrier metal layer generally include a refractory material such as MoSi.sub.x (molybdenum silicide), WSi.sub.x (tungsten silicide), or the like, and TiN (titanium nitride). The refractory materials are deposited by a sputtering method, and the TiN is deposited by nitriding titanium or by a reactive sputtering method.
After the barrier metal layer is formed, an aluminum alloy layer is deposited on its entire surface. Known photolithography and etching techniques are applied to the aluminum layer to form fine interconnection layers that extend between the diffusion regions of the different transistors, and to bonding pad regions on the isolation layer. An exterior insulating layer for protecting the integrated circuit from the outside atmosphere and mechanical damage, is then applied. Openings are provided in the protection layer at the bonding pad regions to expose the interconnection layer so that leads may be affixed.